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14px;">隨著半導(dǎo)體工藝、芯片規(guī)模的限制越來越大，傳統(tǒng)的單個大芯片策略已經(jīng)行不通，小芯片(Chiplet)成為新的方向，AMD無疑是其中的佼佼者，銳龍、線程撕裂者、霄龍三大產(chǎn)品線都在踐行這一原則，并且取得了不俗的效果。現(xiàn)在，AMD要把這一策略延續(xù)到GPU顯卡上了。</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">2020年的最后一天，AMD向美國專利商標局提交了一項新專利，勾勒了未來的GPU小芯片設(shè)計。</span></p><p style="text-align: center; text-indent: 2em;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726776143222.png"/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">圖：小芯片（Chiplet），AMD已經(jīng)玩兒得很溜</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">AMD首先指出，傳統(tǒng)的多GPU設(shè)計存在諸多問題(包括AMD自己的CrossFire)，比如GPU編程模型不適合多路GPU，很難在多個GPU之間并行分配負載，多重GPU之間緩存內(nèi)容同步極為復(fù)雜，等等。</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">AMD的思路是利用“高帶寬被動交聯(lián)”(highbandwidthpassivecrosslink)來解決這些障礙，將第一個GPU小芯片與CPU處理器直接耦合在一起(communicablycoupled)，而其他GPU小芯片都通過被動交聯(lián)與第一個GPU小芯片耦合，而所有的GPU小芯片都放置在同一個中介層(interposer)之上。</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">這樣一來，整個GPU陣列就被視為單獨一個SoC，然后劃分成不同功能的子芯片。</span></p><p style="text-align: center;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726799585919.png"/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">傳統(tǒng)的GPU設(shè)計中，每個GPU都有自己的末級緩存，但為了避免同步難題，AMD也重新設(shè)計了緩存體系，每個GPU依然有自己的末級緩存，但是這些緩存和物理資源耦合在一起，因此所有緩存在所有GPU之間依然是統(tǒng)一的、一致性的。</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">聽起來很難懂對吧？確實如此，畢竟一般在專利文件中，廠商往往都會故意隱藏具體設(shè)計細節(jié)，甚至可能存在一些故意使之難以理解、甚至誤導(dǎo)的描述。</span></p><p style="text-align: center;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726808382673.png"/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">AMD沒有透露是否正在實際進行GPU小芯片設(shè)計，但早先就有傳聞稱，下一代的RNA3架構(gòu)就會引入多芯片，這份專利正提供了進一步佐證。</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">可以預(yù)料，RDNA3架構(gòu)如果真的上小芯片設(shè)計，核心規(guī)模必然會急劇膨脹，一兩萬個流處理器都是小意思。</span></p><p style="text-align: center;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726820240123.png"/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">AMD也不是唯一有此想法的人。IntelXeHP、XeHPC高性能架構(gòu)就將采取基于Tile區(qū)塊的設(shè)計，今年晚些時候問世，直奔高性能計算、數(shù)據(jù)中心而去。</span></p><p><br/></p><p style="text-indent: 2em;"><span style="font-size: 14px;">NVIDIA據(jù)說會在Hopper(霍珀)架構(gòu)上采用MCM多芯封裝設(shè)計，而在那之前還有一代“AdaLovelace”(阿達·洛夫萊斯)，有望上5nm工藝，并堆到多達18432個流處理器。</span></p><p style="text-align: center;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726831140864.png"/></p><p style="text-align: center;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726839355669.png"/></p><p style="text-align: center;"><img alt="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? title="AMD申請小芯片專利：RDNA3或?qū)⒈┝Χ押? src="/static/upload/image/20210104/1609726846102788.png"/></p> </div> <div id="wzheybu" class="text-secondary lh-2 nm-page"> <span>上一篇：<a href="/hyxw/638.html">3分鐘讀懂PCB原理圖的反推全過程</a></span> <span>下一篇：<a href="/hyxw/640.html">盤點高頻PCB設(shè)計中的小竅門</a></span> </div> <div id="6xqdxa8" class="nm-keywords"> <b>此文關(guān)鍵字：</b> </div>  <div id="ngy8hyr" class="nm-about-zixun"> <h3 class="nmaz-title">相關(guān)咨詢</h3> <div id="03teru4" class="nmaz-con"> <ul> </ul> <div id="nerju8u" class="clear-fudong"></div> </div> </div>  <div id="o2aihkd" class="nm-tuijian-fuwu"> <h3 class="nmtf-title">推薦服務(wù)</h3> <div id="c3czm9t" class="nmtf-con"> <ul> <li> <a href="/dpjyjkf/" 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